US Patent No: 4,835,705

Number of patents in Portfolio can not be more than 2000

Interconnection area decision processor

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Abstract

The present invention provides an interconnection area decision processor for deciding vertical widths of areas employed for interconnection of a gate array. The interconnection area decision processor predicts which interconnection area each signal net passes on the basis of previously created data on cell arrangement and data on arrangement of transistor rows on a chip to estimate interconnection congestion per channel on the basis of the result of prediction and decide the number of transistor rows to be assigned to each channel on the basis of the estimated interconnection congestion, thereby to create data on the vertical width of each channel. Thus, density of integration can be improved by increasing the number of tracks of channels having large numbers of interconnections and decreasing the number of tracks of channels having small numbers of interconnections.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
MITSUBISHI DENKI KABUSHIKI KAISHATOKYO19938

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ajioka, Yoshihide Itami, JP 4 139
Fujino, Yasuhiro Tokyo, JP 5 59
Noda, Tomoyoshi Hyogo, JP 1 53
Terai, Masayuki Tokyo, JP 24 67

Cited Art

Patent Info (Count) # Cites Year
 
Bell Telephone Laboratories, Incorporated (1)
4,577,276 Placement of components on circuit substrates 118 1983
 
The United States of America as represented by the Secretary of the Army (1)
4,613,941 Routing method in computer aided customization of a two level automated universal array 85 1985

Patent Citation Ranking

Forward Cites

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