Delay line control system for automatic test equipment
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United States of America Patent
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Jun 6, 1989
Issued Date -
N/A
app pub date -
Dec 21, 1987
filing date -
Jul 2, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A system is disclosed which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information representing the higher order bits of a time delay, while vernier memories store information relating to the lower order bits of the time delay. Offset memories enable storing calibration data. The base delay memory controls at least two counters in independent signal paths, while the vernier and offset memories control appropriate deskew units for further delaying the counter output signal as desired. The system enables sharing of resources, yet eliminates the need for repetitively loading correction data for deskew operations.
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