Importance

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Abstract

An instruction sequencer for programming parallel operations of functional units in response to an instruction stream is shown. The instruction sequencer includes a random access memory for storing instruction segments which program the operations of the functional units. An instruction address register contains instruction addresses for selected locations in the memory having instruction segments stored therein. A memory address circuit reads out an instruction stream comprising instruction segments from the memory in response to the stored instruction address and stores the same in an instruction buffer register. A rotating network, which is operatively coupled to the instruction buffer register, rotates the instruction stream so as to position a selected instruction segment at a predetermined location in a rotating network. A control circuit determines whether the rotating network is required to rotate the instruction stream and, if so, directs the rotating network to position the selected instruction segment at the predetermined location in the rotating network. A first decoding circuit receives and decodes the selected instruction segment to produce a first control signal. A shifting circuit receives the rotated instruction stream and shifts the same an amount equal to at least the width of the selected instruction segment and then applies the same to a second decoding circuit which produces a second control signal. The first and second control signals are adapted to be applied to and commence operation of the functional units in parallel.

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First Claim