Simultaneous multiple level interconnection process
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United States of America Patent
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-
Jun 20, 1989
Issued Date -
N/A
app pub date -
Oct 19, 1988
filing date -
Apr 30, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A system of establishing a conductive via path between spaced interlevel conductors. Successive layers of metallization separated by a dielectric are built. The vias are opened in one step to eliminate interlevel mashing. The system employs annular pads at locations where contact may be established to another wiring level. The vias are self-aligned and taper from top metal to first level contact. The system is applicable both chip-wise and carrier-wise.
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