On-chip bit reordering structure
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United States of America Patent
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Jul 4, 1989
Grant Date -
N/A
app pub date -
Sep 15, 1986
filing date -
Sep 15, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An apparatus and method whereby a static column mode DRAM can access a unique data bit located anywhere within the array chip and sustain a continuous transfer of requested bits in a contiguous group of bits (i.e. block). Steering of the data in a prescribed order is accomplished via a special steering and gating network. A control line, toggle, is used on both rising and falling edges to produce this gapless transfer.
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