High-speed data latch with zero data hold time
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United States of America Patent
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-
Jul 4, 1989
Grant Date -
N/A
app pub date -
Jan 22, 1988
filing date -
Jan 22, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A data latch with substantially zero hold time and with immunity to input data changes occurring after the latch has slewed toward a definable logic state. An input data flip-flop (10) is coupled via transfer transistors (40, 42) to an output data flip-flop (12). Output nodes (36,38) of the output data flip-flop (12) are prechargeable. Inhibit transistors (24,30) are cross-coupled between the input data flip-flop (10) and the output data flip-flop (12) to prevent input data changes from affecting the latch once the output data flip-flop (12) slews toward a definable stable state.
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