Pipelined memory chip structure having improved cycle time
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United States of America Patent
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Jul 4, 1989
Grant Date -
N/A
app pub date -
Aug 17, 1987
filing date -
Aug 17, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor random access memory chip wherein the cycle time is less than the access time for any combination of read or write sequence. The semiconductor random access memory chip is partitioned into relatively small sub-arrays with local decoding and precharging. The memory chip operates in a pipelined manner with more than one access propagating through the chip at any given time and wherein the cycle time is limited by sub-array cycles wherein the cycle time is less than the access time for a memory chip having cycle times greater than access times for accesses through the same sub-array. The memory chip also incorporates dynamic storage techniques for achieving very fast access and precharge times.
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