Process for fabricating compliant layer board with selectively isolated solder pads
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United States of America Patent
Stats
-
Jul 11, 1989
Grant Date -
N/A
app pub date -
Mar 21, 1988
filing date -
Mar 21, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A modified printed wiring board for reducing the cracking of solder joints used to attach ceramic leadless chip carriers to the surface of the printed wiring board. A relatively thin expansion layer is provided on top of the conventional printed wiring board. This expansion layer is bonded to the printed wiring board except at locations underneath the footprint of the chip carrier and solder joints. This expansion layer reduces the stress on solder joints between the ceramic leadless chip carrier and the printed wiring board due to thermal expansion mismatch, to thereby reduce cracking of the solder joint. Prevention of bonding underneath the chip carrier footprint is provided by a thin layer of polytetrafluoroethylene (PTFE). Methods for applying ther PTFE layer are disclosed.
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