Macro structural arrangement and method for generating macros for VLSI semiconductor circuit devices
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United States of America Patent
Stats
-
Jul 18, 1989
Grant Date -
N/A
app pub date -
Jun 19, 1987
filing date -
Jun 19, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A macro generation method and a macro structural arrangement are provided for a VLSI semiconductor circuit device. A circuit macro is defined by a plurality of circuit blocks including at least one control block and an identified number of storage blocks. The control block includes a control section, a bit decoder section, a word decoder section and a work selector section. Each of the storage blocks includes a memory section, a bit selector section and a sense latch driver section. One of a plurality of stored predetermined bit decoders is selectively provided for the bit decoder section. A required number of storage blocks is identified responsive to the selected bit decoder for the selected number of bits per word. A required number of word selectors and memory array subsections is identified responsive to the selected bit decoder for the selected number of words.
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