Digital delay unit with interleaved memory
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United States of America Patent
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Jul 18, 1989
Issued Date -
N/A
app pub date -
Mar 17, 1988
filing date -
Dec 14, 1984
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A first memory cell array (84) has an even address space and a second memory cell array 94 has an odd address space. The memory cell arrays (84, 94) are alternately accessed by even address signals generated from an address counter (81) and odd address signals generated from an address counter (91) so that the data stored in the memory cell arrays are alternately read while new input data are written in the accessed memory cells.
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