Instruction prefetching device including a circuit for checking prediction of a branch instruction before the instruction is executed

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United States of America Patent

PATENT NO 4853840
SERIAL NO

07000427

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Abstract

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In a data processing system capable of processing instructions under pipeline control in a plurality of stages including an executing stage, an instruction prefetching device comprises a prediction checking circuit (66, 67) coupled to a predicting circuit (52, 53) and an instruction executing circuit (32, 33, 37, 38) and a prefetch controlling circuit (47, 86) coupled to the predicting circuit and the checking circuit. In one of the stages that is prior to the executing stage, the checking circuit checks whether or not a prediction for a branch destination is correct. If the prediction is correct, prefetch is continued according to the prediction. If the prediction is incorrect prediction, the prefetch is continued according to a correct prediction with the incorrect prediction corrected immediately after the executing stage. Check of the prediction may be for an instruction other than branch instructions, for either an unconditional branch instruction or a branch count instruction, for a branch destination address, or for a branch direction which becomes clear after the executing stage.

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Patent Owner(s)

Patent OwnerAddress
NEC CORPORATION7-1 SHIBA 5-CHOME MINATO-KU TOKYO 108-8001 108-8001

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Shibuya, Toshiteru Tokyo, JP 8 300

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