Data processor with wait control allowing high speed access
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United States of America Patent
Stats
-
Aug 1, 1989
Grant Date -
N/A
app pub date -
Apr 23, 1987
filing date -
Apr 23, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A slave processor adapted to execute a read/write operation in response to a read/write request signal from a master processor, comprises a first circuit for performing a write operation during a predetermined period of time from the moment a first write request signal is made inactive from an active condition. An second circuit is provided for generating, when another access request signal such as a second write request signal or a read request signal is made active during the above predetermined period of time, an active wait signal requiring the master processor to maintain the second access request signal in an active condition. The second circuit also operates to delay an operation indicated by the second access request signal.
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