
US Patent No: 4,855,619
Number of patents in Portfolio can not be more than 2000
Buffered routing element for a user programmable logic device
Stats
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Aug 8, 1989
Issued date -
Nov 17, 1987
filing date -
07/121,963
serial no -
Expired
status
Importance
Abstract
A programmable interconnect for programmably connecting transmission lines which are part of a configurable logic array is combined with a buffer at locations within the logic array where a signal will travel from a low capacitance line to a higher capacitance line. Use of a buffer in this arrangement allows for programmable interconnects controlling the configuration of the logic array to be smaller; consuming less power and providing for faster rise and fall of an output signal even when propagating through a long series of programmable interconnects. Several arrangements for programmably controlling the interconnect are taught. Also taught is a means of achieving a very wide AND gate without the need for cascading smaller devices.
First Claim
Related Publications
International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 4,758,745 User programmable integrated circuit interconnect architecture and test method | 440 | 1986 | |
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| 4,709,173 Integrated circuit having latch circuit with multiplexer selection function | 20 | 1986 | |
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| 4,544,854 Analog switch structure having low leakage current | 14 | 1983 | |
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| 4,371,797 Circuit for decreasing the effect of parasitic capacitances in field effect transistors used in coupling networks | 12 | 1980 | |
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| 4,642,487 Special interconnect for configurable logic array | 396 | 1984 | |