System for scan testing of logic circuit networks
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United States of America Patent
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-
Aug 8, 1989
Grant Date -
N/A
app pub date -
Oct 7, 1987
filing date -
Oct 7, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The integrity of a circuit processing logic signals is verified by use of switching means, including pass transistors, which are selectively varied to provide different test circuit configurations for different modes of operation. The circuit operates in normal, scan, test and data receive modes. During normal operation, the logic signal from the primary circuit is passed directly through a logic test block without the shifting of data in the logic test block.
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