High speed programmable frequency divider and PLL
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 8, 1989
Grant Date -
N/A
app pub date -
Jan 12, 1987
filing date -
Jan 12, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A phase locked loop including a programmable frequency divider with a variable modulus divider (VMD) having two modes of operation, n and n+1, a programmable counter for counting the number of times the VMD divides the input signal and a comparator for comparing the count in the counter to a predetermined number and switching the VMD from the first mode to the second mode when the instant count and predetermined number are equal. The programmable counter provides an output pulse each time the total count equals a selected number. The VMD is a GaAs semiconductor device.
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