Error protected central control unit of a switching system and method of operation of its memory configuration
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 22, 1989
Grant Date -
N/A
app pub date -
Mar 11, 1987
filing date -
Mar 12, 1986
priority date (Note) -
Expired
status (Latency Note)
A preliminary load of PAIR data current through [] has been loaded. Any more recent PAIR data will be loaded within twenty-four hours. |
PAIR data current through []
A preliminary load of cached data will be loaded soon.
Any more recent PAIR data will be loaded within twenty-four hours.
Next PAIR Update Scheduled on [ ] |
Importance
US Family Size
|
Non-US Coverage
|
Patent Longevity
|
Forward Citations
|
Abstract
A multiprocessor central control unit a switching system with a main memory (CMY) including, aside from a tolerable timing slip, synchronously parallel operated memory block pairs (MB3a/MB3b) during normal operation. The main memory (CMY), together with the central processors (BP, CP . . . IOC . . . ), is connected to a central bus system (B:CMY0/CMY1). The data stored in parallel in the memory blocks of the memory block pairs (e.g., MB3a/MB3b) are EDC-protected. The processors have access to the memory block pairs (e.g. MB3a/MB3b). Upon the occurrence of a multiple error in an indicated second memory block (e.g., MB3b) of a memory block pair (MB3a/MB3b), the second memory block (MB3b) is isolated from the bus system (B:CMY0/B:CMY1) via an automatic memory configuration. The first memory block (MB3a) then performs the read and/or write operations alone, while from time to time the data stored in the second memory block (MB3b) are corrected by reading out of the first memory block (MB3a) and writing into the second memory block (MB3b), but during a concurrent write operation to the first memory block (MB3a) the data to be entered is also immediately written into the second memory block (MB3b) under the same address. A synchronously parallel driven configuration processor pair (SpP0/SpP1), the operation of which is EDC or parity-bit checked, is connected directly to the main memory (CMY) rather than over the central bus system for automatic memory configuration.
First Claim
Family
- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- SIEMENS AKTIENGESELLSCHAFT;OREAD LABORATORIES, INC.
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Bitzinger, Rudolf | Munich, DE | 7 | 124 |
Engl, Walter | Feldkirchen, DE | 5 | 122 |
Humml, Siegfried | Penzberg, DE | 3 | 103 |
Schreier, Klaus | Penzberg, DE | 4 | 112 |
Cited Art Landscape
- No Cited Art to Display
Patent Citation Ranking
Forward Cite Landscape
- No Forward Cites to Display
Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
---|
Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
Full Text
Legal Events
Matter Detail
Update Public Data Dismiss Edit SaveRenewals Detail
Edit SaveNote
The template below is formatted to ensure compatibility with our system.
Provide tags with | separated like (tags1|tags2).
Maximum length is 128 characters for Customer Application No
Mandatory Fields * - 'MatterType','AppType','Country','Title','SerialNo'.
Acceptable Date Format - 'MM/DD/YYYY'.
Acceptable Filing/App Types -
- Continuation/Divisional
- Original
- Paris Convention
- PCT National
- With Priority
- EP Validation
- Provisional Conversion
- Reissue
- Provisional
- Foreign Extension
Acceptable Status -
- Pending
- Abandoned
- Unfiled
- Expired
- Granted
Acceptable Matter Types -
- Patent
- Utility Model
- Supplemental Protection Certificate
- Design
- Inventor Certificate
- Plant
- Statutory Invention Reg
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Success
E-mail has been sent successfully.
Failure
Some error occured while sending email. Please check e-mail and try again!
PAIR load has been initiated
A preliminary load of cached data will be loaded soon. Current PAIR data will be loaded within twenty four hours.
File History PDF
Thank you for your purchase! The File Wrapper for Patent Number 4860333 will be available within the next 24 hours.
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully
Important Notes on Latency of Status data
Please note there is up to 60 days of latency in this Status indicator for certain status conditions. You can obtain up-to-date Status indicator readings by ordering PAIR for the file.
An application with the status "Published" (which means it is pending) may be recently abandoned, but not yet updated to reflect its abandoned status. However, an application filed less than one year ago is unlikely to be abandoned.
A patent with the status "Granted" may be recently expired, but not yet updated to reflect its expired status. However, it is highly unlikely a patent less than 3.5 years old would be expired.
An application with the status "Abandoned" is almost always current, but there is a small chance it was recently revived and the status not yet updated.
Important Note on Priority Date data
This priority date is an estimated earliest priority date and is purely an estimation. This date should not be taken as legal conclusion. No representations are made as to the accuracy of the date listed. Please consult a legal professional before relying on this date.
We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level. Upgrade to our Level for up to -1 portfolios!.