Importance

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Abstract

A novel ECL Programmable Logic Array (PLA) is provided which operates as an ECL PLA, having ECL voltage level compatible input and output leads, thereby providing a high-speed PLA. A unique programming means is provided which allows the ECL PLA to be programmed using TTL-compatible programming voltage levels, such as are provided by common and inexpensive prior art TTL PLA programmers. In another embodiment higher speed is achieved by the design of each sense amplifier using emitter function logic such that the sense transistor and load functions a cascode amplifier. In another embodiment a lower power PLA device is achieved by utilizing a switched current source pull down means for pulling down the rows of the PLA array. In another embodiment low power and user convenience is achieved by allowing each pair of output terminals to share a predefined set of product terms. In another embodiment of this invention, each output terminal is capable of having its output polarity programmed, in order to provide either a desired product term, or the inverse of that product term.

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First Claim