Field programmable matrix circuit for EEPROM logic cells

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United States of America Patent

PATENT NO 4866432
SERIAL NO

07198952

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Abstract

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An improved field programmable matrix circuit. The matrix circuit includes a plurality of pairs of input lines having noninverted and inverted inputs. These input lines intersect a plurality of output column lines. A single transistor is used to provide a programmable connection to each column line from both the inverted and noninverted inputs of an input line pair. The transistor has a source, a drain and a gate with either the source or the drain coupled to a voltage potential and the other of the source or the drain coupled to an output column line. The gate is alternately coupled to a noninverted input, an inverted output, or a second voltage potential. The second voltage potential is coupled when it is desired to hold the transistor in an off state.

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Patent Owner(s)

Patent OwnerAddress
ROHM U S A INC149 KIFER COURT SUNNYVALE CA 94086

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Goetting, Erich Cupertino, CA 4 92

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