Semiconductor memory circuit having a delay circuit
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United States of America Patent
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Sep 12, 1989
Grant Date -
N/A
app pub date -
Aug 5, 1988
filing date -
Aug 7, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A semiconductor memory circuit includes a variable delay circuit for delaying write data supplied from an external circuit such as a CPU by a delay time which is variably determined depending on a potential level of a write enable signal which is supplied from the external circuit and enables a write amplifier to write a delayed write data supplied from the delay circuit into a memory cell array.
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