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Abstract

An apparatus and method of synchronizing data systems having different clock frequencies at a particular address. A first device receives first and second parallel data and outputs first serial data at a first particular clock frequency. A second device outputs second parallel data at a second particular clock frequency that is a submultiple at an integer 'n' of the first particular clock frequency. The second parallel data is outputted in groups of 'n' pieces of data. The address is combined with the integer 'n' until the combination passes through a particular numerical value. This produces a first signal representative of the combination passing through the particular numerical value and a second signal representing an offset position less than 'n' relative to the first serial data. The first and second signals control second parallel data to initiate the outputting of the second parallel data in accordance with the first signal and to offset the outputted second parallel data in accordance with the second signal. The offset second parallel data may then be merged with the first serial data beginning at the proper address.

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First Claim