Plastic molded pin grid chip carrier package
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 19, 1989
Grant Date -
N/A
app pub date -
Nov 13, 1987
filing date -
Nov 15, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An improved plastic molded chip carrier package for a semiconductor chip has a plurality of I/O pins arranged on a pin grid array. The pin grid array comprises at least two rows of the I/O pins disposed along the sides of the chip in such a manner that the I/O pins are staggered with respect to those in the other row. The staggered arrangement of the I/O pins makes it easy to provide electrical interconnection between the I/O ports on the chip and the corresponding I/O pins without requiring an elaborate or crowded wiring or connection lines. This is particularly effective when an increased number of the I/O pins are required to be included in the limited area of the chip carrier.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully