Random access memory system with circuitry for avoiding use of defective memory cells
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United States of America Patent
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Sep 19, 1989
Grant Date -
N/A
app pub date -
Aug 12, 1987
filing date -
Dec 13, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A digital computer can write a block of data to a RAM, or read a block therefrom, via a serial/parallel converter which is word serial, bit parallel on the computer side and bit serial on the RAM side. The RAM is addressed by a free-running address counter clocked by clock pulses WCK. A fault masking circuit enables faulty cells in the RAM to be masked out. Data specific to the RAM causes the clock pulses WCK to be selectively gated for providing bit rate clock pulses GCK to the converter. These pulses are divided down to produce pulses BCK at word rate. The invention is particularly useful in a wafer scale integrated circuit comprising a large number of RAMs served by a single fault masking circuit with tabulated data defining the memory cells to be masked out on a memory by memory basis.
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