Standard cell system large scale integrated circuit with heavy load lines passing through the cells
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United States of America Patent
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Sep 26, 1989
Grant Date -
N/A
app pub date -
May 15, 1987
filing date -
Aug 6, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
This invention relates to a standard cell system large scale integrated circuit which comprises arraying a plurality of standard cells that are equally dimensioned in at least one direction and interconnection said standard cells so as to constitute a logic device, whereby the improvement is characterized in that wiring carrying a heavy load and being connected at many places on the surface of the chip is located within each of the standard cells, furthermore said wiring carrying a heavy load and being connected at many places on the surface of the chip is a clock line, and said clock line is located between a power line and a grounding conductor provided within each standard cell.
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