Method for making silicide interconnection structures for integrated circuit devices
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United States of America Patent
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Oct 10, 1989
Issued Date -
N/A
app pub date -
Nov 8, 1988
filing date -
Jun 15, 1984
priority date (Note) -
Expired
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Abstract
A method for forming a contact to a selective region of an integrated circuit characterized by the steps of: forming a layer of refractory metal over and around the selected region; forming a layer of amorphous silicon over the layer of refractory metal; patterning the amorphous silicon into an elongated strip which extends away from the selected region; annealing the integrated circuit to convert the strip of amorphous silicon into a silicide path; and removing the unreacted refractory metal. The method of the present invention can be used to extend a contact to the source, drain, or gate of a MOSFET from the top of an adjacent section of field oxide, and can also be used as a method for local interconnection of IC devices, such as CMOS devices.
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