Multiple processor accelerator for logic simulation
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United States of America Patent
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Oct 10, 1989
Grant Date -
N/A
app pub date -
Jun 26, 1987
filing date -
Jun 26, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Computer for implementing an event driven algorithm which utilizes a master processor and a plurality of processors arranged in modules, wherein the processors within the module are capable of operating independently of each other. The various modules are also capable of operating independently of each other and communicate with each other and the host unit by a unidirectional token ring bus. A specialized hardwired processor design is implemented to provide a pipelined flow of data to provide a more rapid algotithm simulation.
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