Message FIFO buffer controller
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 10, 1989
Grant Date -
N/A
app pub date -
Oct 15, 1987
filing date -
Oct 14, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A FIFO (first in first out) control circuit for providing address information to a FIFO memory uses two up counters--one to provide the write address and one to provide the read address. A multiplexer selects which addresses (read or write) are used. Two storage registers are used to temporarily 'hold' the output from the counters. This enables the counters to be re-loaded with their original 'count' to enable either a re-reading or a re-writing of a message stored in the FIFO memory. Comparators and logic circuitry are used to provide two status output signals, namely full (or not) and empty (or not).
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully