Alternate memory addressing for information storage and retrieval
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United States of America Patent
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Oct 17, 1989
Grant Date -
N/A
app pub date -
Mar 18, 1987
filing date -
Mar 18, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An apparatus for alternate memory addressing of a random access memory (RAM) allows a first processor to write into the memory on a row-by-row basis and a second processor to read out of the memory on a column-by-column basis. The memory is typically divided into a pluralilty of channels into which the first processor writes data for respective channels asynchronously by the use of twin RAMs. While one RAM is written to by the first processor, the second RAM is read from synchronously with automatic address translation.
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