Method and apparatus for image processing with fed-back error correction

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United States of America Patent

PATENT NO 4878125
SERIAL NO

07140029

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Abstract

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There is an image processing apparatus for digitally processing an image. This apparatus comprises: a binarization circuit to binarize image data by a predetermined threshold value; a processor to correct errors generated in binarization; a first detector to detect an edge direction of the image from the image data; and a second detector to detect an edge quantum of the image from the image data. The process corrects the error data in accordance with the edge direction detected by the first detector or the edge quantum detected by the second detector. The errors to be corrected by the processor are the errors between the output concentration data after the binarization and the image concentration data. The processor adds weight coefficients to the error data in a predetermined range stored in a memory and then adds the weighted error data to image data to be newly binarized. The sum of the weight coefficients which are used in the weighting process is set to '1'. With this apparatus, a high quality apparatus can be reproduced with a high fidelity from an original including many edges.

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Patent Owner(s)

Patent OwnerAddress
CANON KABUSHIKI KAISHA A CORP OF JAPAN30-2 3-CHOME SHIMOMARUKO OHTA-KU TOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hosokawa, Hiroshi Yokohama, JP 179 3719
Katayama, Akihiro Kawasaki, JP 249 4341
Ohsawa, Hidefumi Urawa, JP 36 933
Sunohara, Izuru Ichikawa, JP 3 151
Yoshimoto, Masahiko Yokohama, JP 50 1912

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