Static ram with common data line equalization
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United States of America Patent
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Oct 31, 1989
Grant Date -
N/A
app pub date -
Jan 25, 1988
filing date -
Jan 25, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A static random access memory having a plurality of pairs of common data out lines. A plurality of bit line pairs are coupled to each pair of common data out lines. The common data out lines are automatically equalized at the end of each memory access cycle, and the accessed bit lines are automatically equalized at the end of each write cycle. Thus, the process of equalizing the common data out lines is removed from the critical timing path for accessing the memory, which eliminates one of the primary problems in the use of address transition detection in static memory devices.
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