Semiconductor non-volatile memory with cut-off circuit when leakage occurs
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United States of America Patent
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Oct 31, 1989
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N/A
app pub date -
Sep 19, 1988
filing date -
Sep 19, 1987
priority date (Note) -
Expired
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Abstract
A semiconductor non-volatile memory device includes: a memory cell array having a plurality of memory cells, each including a non-volatile memory cell portion; a high voltage generating circuit for generating a high voltage required for storing data; a plurality of high voltage wirings, each being allocated to each of a corresponding plurality of blocks divided into units of a predetermined number of cells in the memory cell array and being commonly connected to all of the cells in a corresponding block; and a plurality of high voltage feeding circuits, each feeding the high voltage from the high voltage generating circuit to the cells in the corresponding block, and when a leak occurs in any one of the cells in the corresponding block, stopping the feed of the high voltage. By feeding the high voltage separately to each of the blocks divided into units of a predetermined number of cells, a highly reliable store operation can be realized, and if an ECC circuit is mounted, the ECC relief effect can be increased.
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