Method and apparatus for error correction

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United States of America Patent

PATENT NO 4881232
SERIAL NO

07152472

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An error-correcting method and apparatus for a block of data provided with an error-correcting parity for error correction and an error-checking parity that can be used to generate a syndrome for error-checking, in which error correction is carried out by the use of the error-correcting parity and then an error check is carried out by the use of the error-checking parity thereby to increase the reliability of the error-checking data, wherein error information produced by the error-correction process using the error-correcting parity is utilized to correct the syndrome used in the error-checking process, so as to execute the respective operations in parallel and reduce the required data processing time or through-put.

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Patent Owner(s)

Patent OwnerAddress
SONY CORPORATION A CORP OF JAPAN7-35 KITASHINAGAWA-6 SHINAGAWA-KU TOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Sako, Yoichiro Tokyo, JP 702 12171
Yamamura, Shinichi Tokyo, JP 49 1204

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