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Abstract

A logic design automation system examines correspondence relationship among sublogics in intermediate gate-level logic (containing neither physical design information nor manually optimized logic design information) produced from updated functional-level logic and current gate-level logic (containing the above information) to identify corresponding sublogics and non-corresponding sublogics of the gate-level logics with reference to primary input/output signals and input/output gates. For the corresponding sublogics, the corresponding sublogics of the current gate-level logic are selected, and for the non-corresponding sublogics, the non-corresponding sublogics of the intermediate gate-level logic are selected. The selected sublogics are combined to synthesize updated gate-level logic which preserved therein the physical design information and the manually optimized logic design information for portions of the current gate-level logic which need not be modified.

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