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Abstract

This digital processing circuit or sequence includes means (10, 16) of sampling an analog signal and of converting the acquired samples into digital form, a shift register (25), means (23) of storing a value (N.sub..xi.) of an integration constant, a unit (30), an accumulator (31) and a sequencer (14) which controls the sampling and the conversion into digital form of the samples by the said means during a measuring period, the storage of the said digital value representing the last sample acquired in the shift register (25), the operation of the said unit (30) as an adder during the measuring period for the computation of a cumulative sum and, at the end of the said period, the operation of the unit (30) as a subtractor and the operations of rotation of the content of the accumulator (31) in order to divide the final result of the cumulative sum by the value (N.sub..xi.) of the integration constant.

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First Claim