Staggered refresh for dram array
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United States of America Patent
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-
Dec 12, 1989
Grant Date -
N/A
app pub date -
Dec 15, 1987
filing date -
Dec 15, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
According to the present invention, each successive refresh to the multiple banks of a DRAM array is staggered by one clock period. Thus, the time required to refresh one row in each DRAM of each bank at 10 MHz, for example, is equal to 0.7 .mu.sec., or 4.4% of the total allowable maximum time between refresh cycles. This staggered refresh technique avoids large power supply current spikes while minimizing the effect on memory access bandwidth.
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