US Patent No: 4,890,224

Number of patents in Portfolio can not be more than 2000

Method and apparatus for fault tolerant communication within a computing system

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Abstract

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A method and apparatus for fault tolerant communication among a plurality of I/O controllers and a communication controller using an I/O bus having byte-parallel and bit-serial data lines. Each controller is connected to the bit-serial and byte-parallel data lines and the CPU communication controller is capable of selectively indicating which set of lines shall be used for communicating information. When serial communication is desired, a switching signal is transmitted by the CPU communication controller on the serial data line whereupon the I/O controllers switch communication from the byte-parallel data lines to the bit-serial data line. Serial arbitration conflicts are avoided by allocating a time interval to each I/O controller. Each time interval is divided into 3-bit periods. An arbitrating I/O controller asserts the first itself bit true, asserts the second bit false, and disconnects from the bus during the third bit period to separate in time the modules connected to the bus from each other. The CPU communication controller in an operating system initializes newly-inserted modules and synchronizes unsynchronized modules by generating a signal on the bus for prescribed periods of time after which synchronizing control modules within each I/O controller synchronizes the I/O controller with the rest of the system.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
HEWLETT-PACKARD COMPANYPALO ALTO, CA2952

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fremont, Michael J Palo Alto, CA 4 208

Cited Art Landscape

Patent Info (Count) # Cites Year
 
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Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
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