Parallel processing system with processor array having SIMD/MIMD instruction processing
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United States of America Patent
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Jan 2, 1990
Grant Date -
N/A
app pub date -
Dec 17, 1986
filing date -
Dec 17, 1986
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and are controlled by a central processing unit. Each processing element includes a memory, and all of the memories in the processing elements form at least part of the memory available to the CPU. The processing elements normally execute programs in MIMD mode, and the CPU or another unit can interrupt them to execute a SIMD instruciton. The network allows for transmission of variable length messages and also for combining messages when received at a common processing element.
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