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Abstract

A time division multiplexer is operable to sample data on parallel input channels at a sampling rate at least twice the data rate, to serially transmit the data for each channel in a respective time division, and to recover the data at a receive end. The multiplexer is provided with a bit storage register for successive samples on at least one input channel to be used as a marker channel. Gating connected to the bit storage register forces a detectable unnatural data pattern on the transmitted data for that channel whenever a predetermined bit pattern is stored for that channel. According to one embodiment, when a plurality of unchanged levels (e.g., binary one) appear in the bit storage register, a central bit is inverted to thereby mark that channel. The inverted marker bit is detected and cancelled at the receive end and/or is used to reset the channel counter if detected on a channel other than the marker channel.

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First Claim