Importance

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Abstract

A computer system including a first computer unit processing user's tasks, a second computer unit performing a halt operation for a virtual memory access, a main memory storing a plurality of virtual accessing data, a buffer memory unit temporarily storing a part of the virtual accessing data and having a faster operation time than that of the main memory, and a control unit controlling the above. The buffer memory unit receives a virtual memory address from the first computer unit and outputs a corresponding actual memory address for accessing the main memory. The control unit includes first and second latches and outputs a bi-state interruption signal and a multilevel interruption signal in response to states of the first and second latch circuits. The first latch is set when a corresponding virtual access data is invalid so that the second computer unit is operated in response to the bi-state interruption signal to store a corresponding virtual access data in the main memory unit into the buffer memory unit. The second latch is set when the corresponding virtual access data in the main memory unit to be stored into the buffer memory unit is erroneous so that the multilevel interruption signal is output from the control unit to the first computer unit to terminate the operation of the virtual memory access.

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First Claim