Dual-port memory with inhibited random access during transfer cycles
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United States of America Patent
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Jan 30, 1990
Issued Date -
N/A
app pub date -
Jun 18, 1987
filing date -
Dec 30, 1983
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.
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