Semiconductor memory device having serial writing scheme
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United States of America Patent
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Feb 6, 1990
Grant Date -
N/A
app pub date -
Dec 29, 1986
filing date -
Dec 26, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An improved semiconductor memory which can achieve high-speed data processing is disclosed. The memory comprises a memory array, a random access port for accessing a desired one of memory cell in accordance with row and column addresses, a serial read circuit for consecutively reading data from the selected row one by one and a serial write circuit for consecutively writing data to the selected row one by one without specific column address information.
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