Process for making polysilicon field plate with improved suppression of parasitic transistors
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United States of America Patent
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Feb 13, 1990
Grant Date -
N/A
app pub date -
Dec 21, 1987
filing date -
Dec 21, 1987
priority date (Note) -
Expired
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Abstract
A method of forming silicon integrated circuits offers radiation resistance together with a high degree of planarity, including a thin field oxide together with a set of conductive plates over the field region combine to suppress the formation of parasitic transistors. In one embodiment, a silicon substrate is etched to form trenches and is then covered with a thin barrier layer, (410) of high quality thermal oxide. A polysilicon layer (423) is next conformally deposited and planarized until the barrier layer (410) is exposed, followed by an oxidation step for isolation or gate oxide formation.
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