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Abstract

A data processor includes a reconfigurable arithmetic logic unit (ALU), which includes three ALU portions. One ALU portion includes two 16-bit input ports and a 16-bit output port. The other two ALU portions each include two 8-bit input ports and an 8-bit output port. A reconfigurable 16-bit register file is coupled to the inputs of the ALU portions. Switches couple carry output terminals of the second and third ALU portions to carry input terminals of the first and second ALU portions, respectively. With both switches conductive, a 32-bit ALU is formed from the three portions. With a first switch open, two independent 16-bit ALUs are formed. With the second switch open and the first closed, 24-bit mantissa, 8 bit exponent floating-point processing can be done by independent ALUs. The output of the first ALU portion loops back by a first multiplexer to a first 16-bit input of a register, and the two 8-bit outputs of the second and third ALU portions loop back by a second multiplexer to a second 16-bit input of the register. The register output couples words to be processed to the ALU portions.

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