Importance

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Abstract

A circuit for assisting the charging of a line conductor having a distributed resistance and capacitance, such as a word line in a semiconductor memory device, is disclosed. In the conventional memory device, a driver circuit is disposed at one end of a word line, with a circuit for holding unselected word lines at the discharged voltage being disposed at the end of the word line opposite from the drive circuit. The invention is directed towards a pull-up circuit being disposed at the end of the word line opposite the driver circuit, the pull-up circuit having a transistor which is precharged to a high voltage prior to the active cycle. The precharged transistor is discharged as the selected word line is charged by the driver circuit, causing a driving node in the circuit to be connected to a high supply voltage. The driving node is connected to the word line by a transistor which is responsive to a select signal generated by the address decoder; once selected, the word line at the end opposite the driver circuit is driven by the high supply voltage. This will enable the selected word line to be pulled up to the high supply voltage at both ends, thereby reducing the time required to charge the word line to the required voltage level. The pull-up circuit may also include a transistor for holding the word line low, if unselected; this transistor is made non-conductive as the precharged transistor is discharged. Further disclosed is a circuit which allows a plurality of word lines to share the precharging and driving transistors, but which dedicates for each word line the 'bleeder' transistor for holding unselected word lines low and the transistors for coupling the driving node to the word line. In addition, a circuit which provides a reduced voltage at the bleeder transistor, thereby speeding up the charging of the word line by the driver circuit, is disclosed.

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First Claim