Dynamic random-access memory system with power-up and power-down refresh circuits
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United States of America Patent
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Feb 13, 1990
Grant Date -
N/A
app pub date -
Nov 2, 1988
filing date -
Jan 22, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A dynamic random-access memory (DRAM) has a first refresh circuit for producing memory refreshes during power-up, and a second refresh circuit for producing memory refreshes during power-down. The power-down refresh circuit is powered by a battery, and has a lower power consumption than the power-up circuit. During transition from power-down to power-up, the frequency of refreshing is doubled for a short period, so as to build up a surplus of refreshes. This allows refreshing to stop while the first or power-up refresh circuit is brought back into operation.
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