Importance

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Abstract

A time slot interchange matrix is comprised of a plurality of matrix modules (50-56) each for receiving data on a plurality of channels and transmitting data on the same number of channels. Each of the modules consists of separate banks of random access memory that are interfaced with an intramatrix bus (70) for receiving data from each of the matrix modules in the system for storage therein during a collection frame. During a transmission frame, this information is randomly accessed in accordance with an interconnect pattern stored in a control RAM (122) for output from the digital matrix module. Each digital matrix module stores all of the information in the system such that the system is non-blocking for any given channel stored such that information is not impeded by the interconnect pattern of another digital matrix module. A digital bridge (80) is provided for collecting the information during a collection frame and then accumulating the information in a bridge IC circuit (137) as a conference. The accumulated information is stored in a RAM (406) and then output during the transmission frame to the individual conferees in a conference. Echo cancelling is provided by storing the conferee data in conference RAMS (344) and (346) for subtraction in a subtraction circuit (408) during the transmission frame.

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First Claim