Memory bank selection arrangement generating first bits identifying a bank of memory and second bits addressing identified bank
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United States of America Patent
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Feb 20, 1990
Grant Date -
N/A
app pub date -
Feb 27, 1987
filing date -
Feb 27, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory bank selection arrangement has a memory which is made up of smaller memories each of which has a number of banks of memory. First bits of a memory address are used by an address controller for addressing a location in a selected bank of a first of the smaller memories. The address may be incremented by the controller before being used to address a second of the smaller memories, and a carry output is generated when the first bits are incremented and there is a carry from the highest order bit thereof. The memory address also includes second bits which are input to an adder which increments the number represented by the second bits responsive to the carry out from the controller to compensate for the incrementation of said first bits. The incremented or unincremented number output from the adder is used by a selector to select a bank of the smaller memories so that they can be addressed using the incremented or unincremented first bits.
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