Importance

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Abstract

The essence of the invention is a socalled 'data bit variable spacer generator', block 79, which contributes to the generation of a control output 'c' from a combinatory logic circuit group 78. The logic level of 'c' determines whether a clear data bit from the parity flip flop FF6 is to be sent out or a random bit from block RMG. The `variable data bit generator` is controlled by a number of parallel bit outputs from registers SH1 and SH2 which hold an encryption key after being conditioned by other logic inputs derived from key parity flip flops (FF1 and FF2) and clear data bit levels from block 81. Registers SH1 and SH2 shift and recirculate when the `c` output is high. Similar principles are used when data are decrypted. The circuit is suitable for integration with other functions on a single substrate chip.

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First Claim