Dual-rail processor with error checking at single rail interfaces
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United States of America Patent
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Mar 6, 1990
Grant Date -
N/A
app pub date -
Sep 4, 1987
filing date -
Sep 4, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A dual processor computer system with error checking includes a first processing system for executing a series of instructions including output instructions. A second processing system executes the series of instructions independently of and in synchronism with the first processing system. Shared resource devices are coupled to the first and second processing systems for receiving data from output instructions from the first and second processing systems substantially simultaneously. Error checking devices are located downstream of the shared resource means for checking the data received from the first and second processing systems only following a write operation into the shared resource means.
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