Semiconductor fuse programmable array structure
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United States of America Patent
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-
Mar 20, 1990
Grant Date -
N/A
app pub date -
Dec 29, 1988
filing date -
Dec 29, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A programmable array including FET devices arranged in rows and columns is disclosed in which first and second bit lines for cells in adjacent first and second columns are arranged so that a fusible link connecting a cell of a column to its associated bit line crosses the bit line associated with the adjacent column of cells. By doing so, two fuses may now be located in an area which was heretofore occupied by a single fuse.
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