Flexible VLSI on-chip maintenance and test system with unit I/O cell design
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 27, 1990
Grant Date -
N/A
app pub date -
Oct 23, 1987
filing date -
Oct 23, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
This application describes a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins. The cells function is alterable (to input or output and to where the data input signals originate) by control signals which may originate with a control register. The clock input signal is split into two independent signals to selectively disable the input or output registers, thus allowing the control register to be changed without affecting the contents of the other two registers. An early signal is also provided to prepare for mode changes.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully